Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 100 Volts, while operating at high frequencies, e.g., 100 kHz-10 GHz.
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because of the 2DEG region existing under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
FIG. 1 illustrates a conventional GaN transistor device 100. Device 100 includes substrate 11 composed of silicon (Si), silicon carbide (SiC), sapphire, or other material, transition layers 12 typically composed of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) that is about 0.1 to about 1.0 μm in thickness, Mg doped GaN layer 10, buffer layer 13 typically composed of GaN that is about 0.5 to about 3 μm in thickness, current conducting region 14 composed of GaN or indium gallium nitride (InGaN) typically about 0.01 to about 0.5 μm in thickness, contact region 15 typically composed of AlGaN, Al and titanium (Ti) that may have Si, typically about 0.01 to about 0.03 μm in thickness, barrier layer 16 typically composed of AlGaN where the Al to Ga ratio is about 0.1 to about 0.5 with a thickness of about 0.01 to about 0.03 μm, gate structure 17 composed of a nickel (Ni) and gold (Au) metal contact, and ohmic contact metals 18, 19 composed of Ti and Al with a capping metal such as Ni and Au.
During growth of Mg doped GaN material in a conventional GaN transistor device (e.g., FIG. 1), magnesium (Mg) is added to the growth environment. This Mg accumulates on the surface of the GaN and becomes part of the crystal. In addition, Mg coats the walls of the growth chamber during this part of the growth. Growth of undoped GaN, with the intention of having material without Mg present, following the growth of Mg doped material is difficult due to the presence of Mg still residing on the surface of the GaN and other Mg on the walls of the chamber. This residual Mg will continue to contaminate the crystal for extended lengths of time as Mg moves easily about the growth chamber.
Conventional GaN transistors have many disadvantages. The breakdown voltage is limited by the width of the gate 17 (as shown in FIG. 1). To reach high voltages, a wide gate and large separation between gate 17 and drain contact 18 is required due to residual n-type doping from oxygen contamination and nitrogen vacancies in the undoped GaN material 13. In addition, conventional GaN transistors using Mg doping in the buffer layer suffer from changes in the conductivity caused by Mg near the barrier layer.
It would be desirable to provide a method and apparatus to achieve the improved breakdown of devices utilizing doped buffers, while eliminating the device performance variations caused by dopants near the barrier layer. To achieve this goal, it is desirable to trap excess dopants in order to avoid the above-mentioned disadvantages of the prior art.